A Novel Algorithm of Fundamental Positive Sequence Voltage Detector under Unbalanced and Distorted Voltages

This paper presented a new algorithm for the performance improvement of fundamental positive sequence voltage extraction under unbalanced and distorted conditions. In this algorithm, an improved software phaselocked loop (SPLL) with a second order low-pass filter was proposed and analyzed, completely eliminating the phase detection errors of the unbalanced and distorted source voltages. The paper began with a description of the proposed fundamental positive sequence extraction method, and then a detailed analysis of the designed SPLL was introduced. The proposed algorithm improved the sinusoidal current control strategy of active power filter (APF) which was based on the classical power theories for obtaining an optimal extraction of the fundamental positive sequence current. To verify the feasibility of the algorithm in realtime applications, the simulation model was established in MATLAB-Simulink environment. Then, the algorithm was implemented in DSP using the TMS320F28335 development board. The results indicated that the proposed algorithm is feasible and effective, and it could be directly used in the practical applications.


INTRODUCTION
Harmonic currents and reactive power generated by non-linear loads have a significant adverse impact on electrical distribution systems. The shunt active filter (APF) has been proved to be effective for the elimination of current harmonics and reactive power compensation. One of the cornerstones of APF is its control strategy for the realtime and accurate calculation of reference or compensating signal [1] [2] . Many kinds of control strategies in a shunt active filter have been proposed so far, one of which is the Sinusoidal Source Current Control Strategy based on the pq Theory [3] [4] .
The sinusoidal source current control strategy is a principle of compensation that conducts the active filter to compensate the current of a non-linear load, and finally to achieve the result of making the compensated source current sinusoidal and balanced.
As the most important component in that strategy, the fundamental positive sequence voltage detector aims to improve the compensation performances under all voltages conditions, for example, voltage unbalances or voltage distortions.
For the extraction of fundamental positive sequence voltage, some literature has proposed detecting method based on the concept of space vector [4] or in frequency domain [5] . Reference [6] presented a performance comparison between a SPLL and an adaptive filter for detecting the fundamental positive sequence component. This paper proposes a much simpler algorithm just based on simple mathematics formula of trigonometric function which could be more useful in practice.

SEQUENCE VOLTAGE DETECTOR
For a three-phase four-wire system, when the power system is unbalanced and distorted, the phase voltages contain positive sequence components, negative sequence components, zero sequence components and harmonic components.
Regarding the fundamental positive sequence detection, many extraction methods have been presented during the last years. The simple common methods are based on the detection of the peak value and zero crossing instants. Nevertheless, these methods might lead to significant angle and magnitude errors if facing unbalanced or distorted waveforms [7] .
To solve this problem, we proposed a fundamental positive sequence voltage detector block , which uses a software phase-locked loop circuit locked to the fundamental frequency of the system voltages.
The overall principle block diagram of fundamental positive sequence voltage detector is shown as Fig. 1. It consists of coordinates transformation block, software phase-locked loop and low pass filter. Because the value of zero sequence components after dq transformation is zero, it needn't to be considered [8] .
Where U is the RMS value of source voltages, ! and " are the angular frequency and initial phase angle of source voltages; the subscript 1,2 donate the positive sequence component and the negative sequence component respectively; the subscript n donates the harmonic order(when n equals to 1, it donates the fundamental component ). The three-phase voltages are transformed to #$ two-phase orthogonal coordinate by C 32 , shown as below.
In order to obtain the fundamental component, structure a transformation matrix C T as below.
Where !t+# is the phase angle of phase A getting from the SPLL.
Convert u # and u $ signals to u p and u q through C T , shown as below.
Equation (5) shows that the fundamental positive sequence component corresponds with DC value. Through a low pass filter, the other AC components in (5) could be eliminated and get the following result. 3 cos( ) The fundamental positive sequence of phase A is given as. 2 sin( ) That is, Where sin(!t+#) and cos(!t+#) are acquired from the software phase-lock-loop output and calculated by sine and cosine function. From (8), we know that the fundamental positive sequence of phase A could be extracted by a simple mathematical operation between (6) and sine and cosine value of the phase lock angle. Similarly, calculation formula of phase B and phase C are, III. SPLL PRINCIPLE UNDER UNBALANCED AND

A. Software Phase-locked Loop Working Principle
In grid connected converter applications, PLL is crucial for control algorithm performance [9] . The basic scheme of a classic PLL consists of a phase detector, a voltage controlled oscillator (VCO), a low-pass filter and a comparator [10] . Although the traditional PLL has been widely applied in electronic applications, it is not sufficiently immune to grid voltage variations.
Software implementation has several advantages including easy customization of the feedback loop that could timely change the multiplication or division ratio between the signal being tracked and the output oscillator. Hence, it may make sense to implement a phase locked loop in software for applications under unbalanced and distorted voltage conditions.
The proposed three-phase SPLL, operating in #$ and dq coordinates, is based on a second-order Butterworth lowpass filter. Compared to the classic algorithms, the proposed one is with a different structure, presented in Fig. 2. As shown in Fig. 2, for a three-phase software phaselocked loop, firstly convert voltage signals from abc axis to #$ axis through (2)�and then #$ components are converted into dq rotating axis using (10).
In the transformation matrix�! * t represents the SPLL output. The value of u q reflects the phase difference between the input voltage and the output voltage of SPLL.

PAPER A NOVEL ALGORITHM OF FUNDAMENTAL POSITIVE SEQUENCE VOLTAGE DETECTOR UNDER UNBALANCED…
When u q =0, it is supposed that phase-locked loop has tracked the input voltage phase angle. At this time, ! * t is the phase angle of input voltage.
But if the three-phase voltages are unbalanced and distorted, ! * t will include fundamental positive sequence phase, negative sequence phase and harmonic phase at the same time. In order to acquire the fundamental positive sequence voltage phase only, the value of u q under unbalanced and distorted voltages (shown as (11)) is analyzed and get the conclusions as follows. After dq transformation, angular frequency of the positive sequence component decreases, and fundamental positive sequence component converts into DC value. While angular frequency of the negative sequence component increases, together with other harmonic components as AC value, the negative sequence component and harmonic components could be eliminated by a low-pass filter and get the phase angle !t+# mentioned previously.
Literature [11] stated that SPLL system has a forward integral element, so it is inherently with the certain low pass filtering characteristic. However, when the voltages are distorted and unbalanced seriously, the AC amplitude of negative sequence component and harmonic components after dq transformation are so large that only relying on the filtering characteristic of SPLL can't fully filter all the AC components. So, an additional filter is introduced into the SPLL system. Taking both dynamic response and filtering effect of the filter into consideration, this paper chooses a second-order Butterworth filter.

B. Software Phase-locked Loop Performance Analysis
According to the above parameters, bode diagram of the SPLL system is presented in Fig. 4. The allowed frequency component in q u is usually lower than 2 Hz�therefore, the filter needs to eliminate other higher frequency components. As shown in the bode diagram, when f=50 Hz, system gain is -30 dB and the phase is -157°; when f=100 Hz, the gain is -53 dB and the phase is -174°. These results indicate that this system has good filter characteristics.

A. Model Simulation Results
In order to validate the feasibility of the algorithm, a fundamental positive sequence voltage extractor Simulink model is built to simulate the three-phase voltages with harmonic components and asymmetric components. The extract result of phase A and phase lock result are respectively shown in Fig. 5 and Fig. 6, when source voltages are stacked with 20% five harmonic component and 12% fundamental negative sequence component to simulate distorted and unbalanced situation.
With the analysis of results, it is known that due to the existence of PI regulator and filter, during the first four cycles, phase-locked effect is not well established and frequency is below 50Hz. But only 0.08s later, phaselocked loop realizes the input signal's frequency tracking and phase tracking, and fundamental positive sequence extractor works accurately, extracting phase A fundamental positive sequence voltage signal in real-time. Fig. 7 illustrates the extraction result when the harmonic and negative components disappear. System could still well track and extract corresponding fundamental voltage.
Through the above simulation, it is found that the extractor has fast response speed, good dynamic performance, which can complete the fundamental positive sequence voltage extraction timely and effectively under unbalanced and distorted voltages.

B. Software Validation based on TMS320F28335
TMS320F28335 is a floating-point digital signal processor. It adds a floating point arithmetic kernel to the DSP platform, making it easier to carry out complex floating point arithmetic and greatly save code execution time and storage space. It has much more merits such as high precision, large data and program memory space, together with more accurate A/D conversion, which are advantageous to be embedded in industry applications. Supposed the three-phase voltages are distorted and unbalance, for the convenience of observation, they are given as follows.
Operation results are shown from Fig. 8 to Fig. 11.  Figure 11. The waveform of SPLL output and its corresponding sine value when the system has achieved stability As illustrated in Fig. 8 and Fig. 9, owing to the PI regulator and second-order filter in the SPLL, as well as the filtering link in the fundamental positive sequence extractor algorithm, there were some phase differences between output voltage and input voltage of extractor system during the first few cycles.
Although those processes cause a time delay, the fundamental positive sequence voltage detector still could get an accurate and excellent extract result just after about 4 cycles, as shown in Fig. 10 and Fig. 11. About 4 cycles, SPLL traces into the angle of phase A and realizes its fundamental positive sequence voltage amplitude and phase extraction. The output fundamental frequency is 50 Hz.

V. CONCLUSION
Aimed at meeting requirements of fundamental positive sequence voltage in the sinusoidal current control strategy for APF, this paper introduces a new algorithm of fundamental positive sequence voltage extractor. The extractor algorithm contains a software phase-locked loop with an additional filter, strengthening the phase lock precision and voltage extraction accuracy. It can be used under unbalanced and distorted voltages, accurately extracting system fundamental positive sequence component with the corresponding amplitude and phase. In spite of the time delay, the response accuracy is guaranteed. In practical applications, the system response speed can be adjusted according to actual requirements, and appropriate time compensation can be implemented to make the extractor algorithm further optimization.