Parallel AES Encryption Engine for Many Core Processor Arrays Using Masked S-Box

Authors

  • Dhanya Pushkaran Sree Narayana Gurukulam College
  • Neethu Bhaskar

DOI:

https://doi.org/10.3991/ijes.v2i4.4194

Abstract


With the ever increasing growth of data communication, hardware encryption technology will become an irreplaceable safety technology. In this paper, I present a method of AES encryption and decryption algorithm with 128 bit key on an FPGA. In order to protect “data-at-rest” in memory from differential power analysis attacks with high-throughput advanced encryption standard (AES) engine with masked S-Box is proposed. By exploring different granularities of data-level and task-level parallelism, we map 2 implementations of an Advanced Encryption Standard (AES) cipher with online key expansion on a fine-grained many-core system.

Author Biography

Dhanya Pushkaran, Sree Narayana Gurukulam College

Electronics and Communication

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Published

2014-10-25

How to Cite

Pushkaran, D., & Bhaskar, N. (2014). Parallel AES Encryption Engine for Many Core Processor Arrays Using Masked S-Box. International Journal of Recent Contributions from Engineering, Science & IT (iJES), 2(4), pp. 35–38. https://doi.org/10.3991/ijes.v2i4.4194

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Section

Papers